[libre-riscv-dev] Introduction

[Aleksandar Kostovic]

>
> Btw Aleksander, I just wanted to say that I am very grateful that you want
> to help get this project underway,

;)


>  and that you can do HDL.
> I can *read* HDLs, and I did design a custom ASIC once, with help from an
> associate... the only thing being, we had to design it entirely at the gate
> level (!) by translating the c code version, together.


I started doing HDL in 2017. Could read it but not write it. Than i started
practicing every day by writing all the types of gates and flip flops in
Verilog. Thats how i got the concept and figured out what all those
keywords mean. So pretty strange way, but it worked for me.

Also as you probably saw by now on comp.arch I can do high level design of
> architectures, again, if assisted by experts who really know their stuff.
> That's basically the pattern: as a team we will be able to get this
> processor done, and you bring some critical expertise which is not so much
> what you've already done as it is the ability to adapt and absorb.


This is the beauty of team work. When our knowledge and will is combined,
we can achieve anything. All of you are very knowledgeable and i am glad to
be part of this group.

Luckily, python is pretty clear :) If you are not already using colour
> syntax highlighting I strongly recommend it, the colour triggers one
> hemisphere of the brain and the words trigger the other.


Yeah i already have the colorful syntax highlighting installed and python's
syntax is pretty easy. See image:
-------------- next part --------------
A non-text attachment was scrubbed...
Name: img.png
Type: image/png
Size: 147427 bytes
Desc: not available
URL: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/attachments/20190131/bcc65fd9/attachment-0001.png>