[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

Jacob Lifshay programmerjake at gmail.com
Sun Jan 27 23:38:11 GMT 2019


On Sun, Jan 27, 2019, 08:28 Luke Kenneth Casson Leighton <lkcl at lkcl.net
wrote:

> On Sunday, January 27, 2019, Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> >
> > > The brownfield encoding space may end up being used for future
> > extensions:
> > > xBitManip being the most likely candidate.
> > >
> > From what I saw last time I looked at the public info, they ended up
> using
> > some more of funct7 similar to how the M extension does rather than using
> > something that is different between OP and OP-32
> >
> >
> Good to know.
>
>
> > >
> > > So where are we. 12 bits.
> > >
> > > * 5 bits vlpr5
> > > * 1 for rd (or 2? issue with 32bit ops)
> > > * 1 for rs (or 2?)
> > >
> > you forgot rs2. some ops (shift, mulhsu, sub, div, mod, etc.) are not
> > commutative, so it'd be nice to have both scalar<<vector and
> > vector<<scalar.
>
>
> Ngggh! This is almost impossible.  There is just too much. Seriously
> considering 64 bit space instead.
>
see email sent few min ago.

>
>
> --
> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>


More information about the libre-riscv-dev mailing list