[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Luke Kenneth Casson Leighton]

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On Wed, Jan 23, 2019 at 3:26 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
>
> On Tue, Jan 22, 2019 at 3:10 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > btw jacob i'm not saying "no" to modified instructions (non-RV),
> > especially given that the priority is llvm, where yes we have to
> > maintain a custom version of that: gcc and binutils can be deferred.
> >
> > what i'm saying is: if there's any other way (such as the implicit
> > 0b00-prefix => scalar idea) i'd prefer that to be prioritised.
> >
> Ok, what do you think about requiring the starting register for vectors to
> be aligned by 2?

 yeah that would work.  also, i noticed that the 48-bit prefix is
7-bits long.  why?  that's a precious bit that could be used.

> This would not restrict register allocation that much and
> we could use the left over bit to indicate vector/scalar. To ensure that
> there's enough space for the vector/scalar bits, the scalar register
> numbers have to be in the range x0-x63.

 that in turn means having a bit that distinguishes between scalar and
vector.  so we're back to 2 bits: 1 bit to distinguish the vector
numbering {N} {RV5-bits} {0} where N is 0/1, LSB is zero

> Basically:
> let reg_num = ...;
> let scalar = (reg_num & 1) != 0;
> let reg_num = if scalar {
>         reg_num >> 1
>     } else {
>         reg_num & ~1
>     };
> use_reg(reg_num);

 yeh so... hang on, let me mentally decode tthat... so vector regs are
at numbers {6..1} 0 and scalar regs are at numbers 0 {5..0}.  yeah
that would work.


> This way, we're not removing 1/4 of the vector registers available right
> out of the gate, and we have more scalar registers available.

 yehyeh got it.