[libre-riscv-dev] Instruction sorta-prefixes for easier high-register access

[Jacob Lifshay]

On Tue, Jan 22, 2019 at 3:10 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> btw jacob i'm not saying "no" to modified instructions (non-RV),
> especially given that the priority is llvm, where yes we have to
> maintain a custom version of that: gcc and binutils can be deferred.
>
> what i'm saying is: if there's any other way (such as the implicit
> 0b00-prefix => scalar idea) i'd prefer that to be prioritised.
>
Ok, what do you think about requiring the starting register for vectors to
be aligned by 2? This would not restrict register allocation that much and
we could use the left over bit to indicate vector/scalar. To ensure that
there's enough space for the vector/scalar bits, the scalar register
numbers have to be in the range x0-x63.
Basically:
let reg_num = ...;
let scalar = (reg_num & 1) != 0;
let reg_num = if scalar {
        reg_num >> 1
    } else {
        reg_num & ~1
    };
use_reg(reg_num);

This way, we're not removing 1/4 of the vector registers available right
out of the gate, and we have more scalar registers available.

Jacob Lifshay