[libre-riscv-dev] berkeley-softfloat-3 implements different variants of IEEE754

[Luke Kenneth Casson Leighton]

ok so a bit of a pain: softfloat-3 actually implements compatibility
with different *hardware* variants of the IEEE754 standard.  there are
three (2 of which have sub-variants): Intel x86 (and an SSE
sub-variant), ARM-VFP2 (and a sub-variant) and RISC-V.

RISC-V returns canonical (default) NaNs rather than do what x86 does,
which is to preserve *some* information when values are added to
non-canonical NaNs.  hence the weirdness for example of putting the
MSB of the mantissa into the LSB when adding positive-zero to a
non-canonical NaN.

this makes life a bit of a pain in the ass, as far as generic
implementation goes.  if either operands are NaN, x86 requires that a
NEGATIVE canonical NaN be returned, whereas RISC-V requires a POSITIVE
canonical NaN to be returned (actually, x86 may be a bit more complex
than that).

either way, we have to choose:

* do we implement RISC-V *only*
* do we implement an option to comply with x86 variations on the
IEEE754 standard

in particular this makes testing complex: you actually have to compile
*special versions* of sfpy with -DSPECIALIZE_TYPE=RISCV (or other
variant).

l.