[libre-riscv-dev] IEEE754 FPU

[Jacob Lifshay]

On Sun, Feb 17, 2019, 10:12 Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> I have finished the module. Now Luke please go over it and find any
> mistakes. I left the commented Verilog code for you to see if there is
> anything that needs to be changed.
>
> Also, what's up with the indentation in python? Getting error messages just
> because something is not indented properly.

python is based on using indentation rather than {...} or begin ... end to
determine block structure.

> For real? Definitely not a
> language i would like to use outside of migen/nmigen. Also autocompletion
> FTW! Without it, I would do this for 20% more time at least.
>
> On Sun, Feb 17, 2019 at 4:08 PM Aleksandar Kostovic <
> alexandar.kostovic at gmail.com> wrote:
>
> > Okay so i made a mistake. In my most recent git commit i started to do
> > things "the hard way". I just literaly found out that functions like
> is_nan
> > or is_zero can just be applied to the m.d.sync. It is a real time saver!
> > Will re-do the module now!
> >
> >
> > On Sun, Feb 17, 2019 at 3:29 PM Luke Kenneth Casson Leighton <
> > lkcl at lkcl.net> wrote:
> >
> >> ok i added a single-cycle variant of the "align" phase, which does a
> >> single-cycle variable-width shift on the mantissa, based on whether
> >> a's exponent is greater than b's (or the other way round).
> >>
> >> what that's allowed is for the align phase to become a stage of a
> >> pipeline.  the downside: i haven't checked the verilog output yet,
> >> however i suspect that the code being generated by yosys is going to
> >> be... um... a *lot* of gates.  there's a huge pause whilst test_add.py
> >> gets set up, which tells me that the simulator is struggling to create
> >> the internal data structures.
> >>
> >> these are some of the things we'll have to be really, really careful
> >> about.  the algorithm for the alignment needs to increase the exponent
> >> (by addition *not* shifting), that's fine, however it needs to not
> >> only shift the mantissa bits downwards, but the bits being shifted out
> >> need to be ORed together to create the sticky bit.
> >>
> >> i chose to do that by shifting a series of all-1s by the same amount,
> >> then inverting it and using it as a mask against the mantissa, and
> >> ORing all of those together.
> >>
> >> it works... it's just going to need a full audit and review.
> >>
> >> l.
> >>
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> >
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