[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

ok i added a single-cycle variant of the "align" phase, which does a
single-cycle variable-width shift on the mantissa, based on whether
a's exponent is greater than b's (or the other way round).

what that's allowed is for the align phase to become a stage of a
pipeline.  the downside: i haven't checked the verilog output yet,
however i suspect that the code being generated by yosys is going to
be... um... a *lot* of gates.  there's a huge pause whilst test_add.py
gets set up, which tells me that the simulator is struggling to create
the internal data structures.

these are some of the things we'll have to be really, really careful
about.  the algorithm for the alignment needs to increase the exponent
(by addition *not* shifting), that's fine, however it needs to not
only shift the mantissa bits downwards, but the bits being shifted out
need to be ORed together to create the sticky bit.

i chose to do that by shifting a series of all-1s by the same amount,
then inverting it and using it as a mask against the mantissa, and
ORing all of those together.

it works... it's just going to need a full audit and review.

l.