[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Sun, Feb 17, 2019 at 7:28 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> no need to actually do the conversion on double_adder.v at all, just
> trust the diff and some common sense.

64-bit divide added as well: i was able to reverse-engineer the
(uncommented) reason for the random-seeming width of the divider unit:
it's double the internally-used mantissa length plus three bits, for
guard / round / sticky.  so for 32-bit that's 2*24 + 3 = 51, and for
64-bit it's 53*2 + 3 = 109

jon's code, during the normalisation phase, adds in the extra "1" into
the mantissa (the "1" that's normally stripped off).  hmm, i should
document that.

only 3 preliminary unit tests added for each of the add64 and div64,
we need a much more comprehensive strategy that adds literally
hundreds of millions of unit tests.  for FP16 it may even be possible
to consider full coverage, given how powerful modern computers are
now.

l.