[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Sat, Feb 16, 2019 at 11:01 AM Aleksandar Kostovic
<alexandar.kostovic at gmail.com> wrote:
> > ok so i was quite annoyed with myself for not letting *you* make the
> > corrections to the code that you'd written, as it actually violates
> > the libre-riscv charter.
>
> You dont have to worry! Its good this way. You correct what i missed and
> that way i actually know what changed. so again no worries.
>
> i've split out the code from the adder into a base class: if you'd
> > like to do multiplier it should be much easier to start from copying
> > the add python code and replacing the special_cases, add_0, add_1
> > stages.
> > i'd like to try doing the divider, if that's ok?
>
> You are so fast! *is not used to this pace*

 sorry, i've been resting a lot, and don't have anything else to do,
so am kiiinda zen'd out :)

> Yeah i will try multiplier and you do devider :)
> We got this!

 awesome.  ok let me commit the divider (not tested), so you have some
sort of idea, you can do a diff on the two python files add and div.

l.