[libre-riscv-dev] IEEE754 FPU

[Aleksandar Kostovic]

I have done the unpack but I have no idea about that TODO stuff. Have a
look at the last few lines I added what would be print Verilog but it
doesnt work. Also see the condition in unpack case. I didnt know what to
use so i put x. i dont know what a 24'h0 in verilog would translate into
something useful by nmigen.

On Thu, Feb 14, 2019 at 3:04 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Thu, Feb 14, 2019 at 9:25 AM Aleksandar Kostovic
> <alexandar.kostovic at gmail.com> wrote:
> >
> > Done. GTG now but when I get back I will try to do another state :)
>
>  ok.  pretty damn good so far.
>
> > BTW, I am happy with what I achieved so far. Nmigen is nothing alike with
> > things I used so far. But I am getting the philosophy of it quickly ;)
>
>  it has quirks, the output from yosys is awful, yet i feel it can be a
> lot clearer, with the use of functions.  also, we can parameterise it
> and the 64-bit and 16-bit versions just drop straight out a single
> class parameter.
>
> l.
>
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