[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

watch out for that one!  off-by-one in the slices.  you got the
inverting right :)  python slices go from start INCLUSIVE to end-point
*EX*clusive... :)

if you run the verilog conversion, then with a lot of arseing-about
identifying what the heck yosys is doing, you can just about identify
the auto-generated verilog and compare it to the original.

that's what i've been doing and have found a few oddities.

l.

--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -237,7 +237,7 @@ class FPADD:

                 with m.If(tot[27]):
                     m.d.sync += [
-                        z_m.eq(tot[4:27]),
+                        z_m.eq(tot[4:28]),
                         guard.eq(tot[3]),
                         round_bit.eq(tot[2]),
                         sticky.eq(tot[1] | tot[0]),
@@ -246,7 +246,7 @@ class FPADD:

                 with m.Else():
                     m.d.sync += [
-                        z_m.eq(tot[3:26]),
+                        z_m.eq(tot[3:27]),
                         guard.eq(tot[2]),
                         round_bit.eq(tot[1]),
                         sticky.eq(tot[0])


On Thu, Feb 14, 2019 at 8:54 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> couple more corrections, aleksander, from doing "python
> nmigen_add_experiment.py generate -t v".  nmigen uses an "Elif"
> keyword for where verilog does "if begin-end else if begin-end else
> begin-end" in nmigen you do "If Elif Else"
>
> --- a/src/add/nmigen_add_experiment.py
> +++ b/src/add/nmigen_add_experiment.py
> @@ -220,14 +220,14 @@ class FPADD:
>                          z_s.eq(a_s)
>                      ]
>                  # a mantissa greater than b, use a
> -                with m.Else(a_m >= b_m):
> +                with m.Elif(a_m >= b_m):
>                      m.d.sync += [
>                          tot.eq(a_m - b_m),
>                          z_s.eq(a_s)
>                      ]
>                  # b mantissa greater than a, use b
>                  with m.Else():
> -                    m.sync += [
> +                    m.d.sync += [
>                          tot.eq(b_m - a_m),
>                          z_s.eq(b_s)
>                  ]