[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

couple more corrections, aleksander, from doing "python
nmigen_add_experiment.py generate -t v".  nmigen uses an "Elif"
keyword for where verilog does "if begin-end else if begin-end else
begin-end" in nmigen you do "If Elif Else"

--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -220,14 +220,14 @@ class FPADD:
                         z_s.eq(a_s)
                     ]
                 # a mantissa greater than b, use a
-                with m.Else(a_m >= b_m):
+                with m.Elif(a_m >= b_m):
                     m.d.sync += [
                         tot.eq(a_m - b_m),
                         z_s.eq(a_s)
                     ]
                 # b mantissa greater than a, use b
                 with m.Else():
-                    m.sync += [
+                    m.d.sync += [
                         tot.eq(b_m - a_m),
                         z_s.eq(b_s)
                 ]