[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Thu, Feb 14, 2019 at 4:31 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> i'll do special_cases later today,

okaaay that's done... aleksander, you want to try the "align" block,
next?  commit it then move on to add_0 if you're comfortable with
that.

ah ha!  https://github.com/nakengelhardt/fpgagraphlib/blob/master/src/faddsub.py

just talking to attie on freenode #m-labs he actually did a FP
multiply / add conversion from verilog to migen.

l.