[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Wed, Feb 13, 2019 at 11:20 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
>
>
> On Thursday, February 14, 2019, Aleksandar Kostovic <alexandar.kostovic at gmail.com> wrote:
>>
>> Changes pushed.
>> Run the python code and it still worked. :)
>
>
> Great . No syntax errors . Try python filename.py generate -t v

... which showed the execution errors (as opposed to python *syntax* errors)

i corrected it as follows:

+        # Signal
+        a_s = Signal()
+        b_s = Signal()
+        z_s = Signal()
+
         guard = Signal()
         round_bit = Signal()
         sticky = Signal()
@@ -72,12 +80,12 @@ class FPADD:
             with m.State("unpack"):
                     m.next = "special_cases"
                     m.d.sync += [
-                        a_m.Cat(self.a[22:0], 0),
-                        b_m.Cat(self.b[22:0], 0),
-                        a_e.Cat(self.a[30:23] - 127),
-                        b_e.Cat(self.b[30:23] - 127),
-                        a_s.Cat(self.a[31]),
-                        b_s.Cat(self.b[31])
+                        a_m.eq(Cat(0,0,0, a[0:23])),
+                        b_m.eq(Cat(0,0,0 b[0:23])),
+                        a_e.eq(Cat(a[23:31]) - 127),
+                        b_e.eq(Cat(b[23:31]) - 127),
+                        a_s.eq(Cat(a[31])),
+                        b_s.eq(Cat(b[31]))
                     ]

so:

* i'd forgotten to add a_s b_s z_z (sign bit)
* not *all* variables are referred to by "self".  only the variables
that are *members of the object*.
* a, b and z are *local* variables; self.a would be a class member,
and there is no such class member "a".
* Cat is imported globally (at the top, "from nmigen import Cat"), it
si not a member of the local variable a_m
* Cat's order of concatenation is done LSB on left to MSB on right
(just as slices are inverted) where verilog goes MSB down to LSB
* the 3'd0 means *three* zero bits need to be concatenated: 0 passed
to Cat means "just one zero bit", so we need *three* zeros.
* i mentioned that python slices are *inverted* compared to verilog,
and that the top number is 1 bigger.  so [30:23] becomes [23:31]
* to assign things to a nmigen variable you need to use {variable}.eq(value).

running the generator-command which uses yosys (you *must* have the
latest version of yosys out of git), it becomes possible to sort-of
check:

  assign \$18  = a[29:23] - (* src = "nmigen_add_experiment.py:85" *) 7'h7f;

BLECH! :)

followed by things like this:

  always @* begin
    \$next\b_e  = b_e;
    casez (fsm_state)
      2'h2:
          \$next\b_e  = \$21 ;
    endcase
    casez (rst)
      1'h1:
          \$next\b_e  = 10'h000;
    endcase
  end

it's all a bit of a mess: each "thing" that is assigned to (m.sync +=)
inside the FSM seems to get its own *separate* case statement
auto-generated.

if that gets sufficiently non-obvious it may be worthwhile just going
back to a case statement and dropping the FSM.  don't know.  have to
talk to people on freenode #m-labs.

i'll do special_cases later today,
l.