[libre-riscv-dev] IEEE754 FPU

[Luke Kenneth Casson Leighton]

On Wednesday, February 13, 2019, Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> unpack does the following:
>         a_m <= {a[22 : 0], 3'd0};  //concatenation operator
>         b_m <= {b[22 : 0], 3'd0};  // again concatenation operator
>         a_e <= a[30 : 23] - 127;   //substracts 127 from exponent
>         b_e <= b[30 : 23] - 127;   //againg substracts 127 from exponent
>         a_s <= a[31];                   //31st bit is assigned to a_s, the
> sign bit
>         b_s <= b[31];                   //^same thing again
>         state <= special_cases;
>
> Now i have some questions. Is there nmigen equivalent of concatenation
> operator?


Cat.  I imported it already, at the top. Look at the code I quoted already.
It's why I said "look at the link". Here it is again:

. you want to try adding the "unpack" state?  it involves using Cat.
. there's some examples here
.
. https://git.libre-riscv.org/?p=rv32.git;a=blob;f=cpu_decoder.py;h=
c92fb8898daea15443b74c506b45efc328ed603e;hb=HEAD




>
>  Also what docs are you using for nmigen?
>
>
Migen docs.




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