[libre-riscv-dev] IEEE754 FPU

[Aleksandar Kostovic]

unpack does the following:
        a_m <= {a[22 : 0], 3'd0};  //concatenation operator
        b_m <= {b[22 : 0], 3'd0};  // again concatenation operator
        a_e <= a[30 : 23] - 127;   //substracts 127 from exponent
        b_e <= b[30 : 23] - 127;   //againg substracts 127 from exponent
        a_s <= a[31];                   //31st bit is assigned to a_s, the
sign bit
        b_s <= b[31];                   //^same thing again
        state <= special_cases;

Now i have some questions. Is there nmigen equivalent of concatenation
operator? Also what docs are you using for nmigen?


On Wed, Feb 13, 2019 at 1:04 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wed, Feb 13, 2019 at 11:26 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > ---
> > crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> >
> > On Wed, Feb 13, 2019 at 10:56 AM Aleksandar Kostovic
> > <alexandar.kostovic at gmail.com> wrote:
> > >
> > > We could try it. I am up for it. In fact, i will start right away.
> Maybe
> > > make a dir in ieee754alu called test and put it there?
> >
> >  test is reserved for... tests :)
> >
> >  added, do a git pull.
>
>  you want to try adding the "unpack" state?  it involves using Cat.
> there's some examples here
>
> https://git.libre-riscv.org/?p=rv32.git;a=blob;f=cpu_decoder.py;h=c92fb8898daea15443b74c506b45efc328ed603e;hb=HEAD
>
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