[libre-riscv-dev] TLB Initial Proposal

[Luke Kenneth Casson Leighton]

On Monday, February 4, 2019, Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Sun, Feb 3, 2019, 23:25 Luke Kenneth Casson Leighton <lkcl at lkcl.net
> wrote:
>
> > On Mon, Feb 4, 2019 at 7:11 AM Daniel Benusovich
> > <flyingmonkeys1996 at gmail.com> wrote:
> > >
> > > Would you know why these messages are not going into the mailing list?
> >
> >  nope.  if you can let me know the exact time and date i can check the
> > exim4 logs.
> >
> i think it's because you have the mailing list set to block images.


No, moderation is set for any message over 40k. I always approve them. You
will receive a response saying "moderation pending".


>
> >
> > > With a grand total input bit count of: 12 bit command/protection + 48
> bit
> > > VMA + 15 bit ASID (rv64 support) + 64 bit PTE (sv48 support) = 139
> bits.
> > > ouchie my spleen.
> >
> that sounds about right for the number of bits of input to the TLB module.
> the number of bits that the CAM is matching on is 36 virtual address bits,
> 1 global bit, and 15 (i think) asid bits.
>
>
Yowser.


> >
> >  that sounds waaay too large.
> >
>
> Jacob
>
> >
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>


-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68