[libre-riscv-dev] TLB Initial Proposal

[Jacob Lifshay]

On Sun, Feb 3, 2019, 23:25 Luke Kenneth Casson Leighton <lkcl at lkcl.net
wrote:

> On Mon, Feb 4, 2019 at 7:11 AM Daniel Benusovich
> <flyingmonkeys1996 at gmail.com> wrote:
> >
> > Would you know why these messages are not going into the mailing list?
>
>  nope.  if you can let me know the exact time and date i can check the
> exim4 logs.
>
i think it's because you have the mailing list set to block images.

>
> > With a grand total input bit count of: 12 bit command/protection + 48 bit
> > VMA + 15 bit ASID (rv64 support) + 64 bit PTE (sv48 support) = 139 bits.
> > ouchie my spleen.
>
that sounds about right for the number of bits of input to the TLB module.
the number of bits that the CAM is matching on is 36 virtual address bits,
1 global bit, and 15 (i think) asid bits.

>
>  that sounds waaay too large.
>

Jacob

>