[libre-riscv-dev] SV / RVV, marking a register as VL.

[Jacob Lifshay]

On Thu, Aug 29, 2019, 04:09 lkcl . <luke.leighton at gmail.com> wrote:

> (taking isadev off cc for this one)
>
> On Thursday, August 29, 2019, lkcl <luke.leighton at gmail.com> wrote:
>
> that would then allow the substituted-instruction to go directly into
> > dependency-tracking *on the scalar register*, nipping in the bud the need
> > for special CSR-related dependency logic, and no longer requiring the
> > sub-par "stall" solution, either.
> >
> >
>  The "cache" idea where a CSRR is rewritten to a MV is the key
> implementation piece of the puzzle that I think means we can go ahead with
> sv.setvl being a pointer-to-a-register rather than a CSR.
>
> Any thoughts on this one, Jacob (to isadev and lrv), any objections, or do
> you need time to think about it?
>
the cache idea sounds like it should work in HW as long as VLPTR is not
rewritten too often. to disable, VLPTR can be set to point to x0.

One concern I have is that implementing a register allocator (and probably
the instruction scheduler too) where there is register indirection may
require rewriting large portions of LLVM, hence why I had proposed
SVPrefix, where all the instructions just had the literal register numbers
and not like SVorig where the CSRs dynamically repointed the registers to
other registers. I guess we can work around this for just VLPTR by always
setting it to point to the same register, but that kinda defeats the
purpose of not just using that register in the first place along with a
VLENABLE csr.

Jacob