[libre-riscv-dev] [Bug 60] N-stage 64-bit multiplier pipeline needed (signed/unsigned)

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=60

--- Comment #23 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
i've put multiply.py and test_multiply.py here:
https://git.libre-riscv.org/?p=ieee754fpu.git;a=tree;f=src/ieee754/part_mul_add;h=af3634054ac530f4fdc7b2877fbf370b9b1bb594;hb=43de8ed4528ea7627cfe2cbac9374074b22687ae

i've started the process of creating modules and using Cat() instead of
individual bit-wise assignment, plus identified some invariants and assigned
them to Signals (_part_byte() is a good example) rather than compute them
multiple times.

even with a (new) module called Term, the graphviz diagram on Mul_8_16_32_64
is innnnsaaaaane.

also, there's 8x8 intermediate product results of 16-bits each behind
Muxes: to save power i believe it should be the case that a and b go
through the Muxes (one each)... *then* the results of that go through
the multiply.

otherwise, the multiply is always active (using power) and there's 64 of them.
that would mean (i believe) that on an 8x 8-bit SIMD, 64 multiplications
would still be performed.

-- 
You are receiving this mail because:
You are on the CC list for the bug.