[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=132

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #14)
> (In reply to Luke Kenneth Casson Leighton from comment #12)
> > (In reply to Jacob Lifshay from comment #11)
> > 
> > > > 
> > > > If the code is not doing single cycle results we cannot use it.
> > > 
> > > yes we can, we just need to tell the pipeline API "this takes 3 stages
> > > instead of one, so insert extra registers on the control signals"
> > 
> > Which still does not take care of cancellation.
> 
> it's a simple data pipe, if a particular element is canceled, that pipeline
> slot will just be empty, just like divpipecore. the control pipeline can
> keep track of which elements have valid data and which have been canceled.
> 
> > 
> > The multiplier code will now need to implement cancellation, which is a
> > global mask (not a register-propagated signal).
> the surrounding control hardware will just set the associated control
> signals such that the canceled/unused data elements are ignored.
> 


Which has the knock on ramifications of underutilised hardware (stages that run
empty) which either decreases the IPC count or requires more RSs to conpensate.

Each RS comes with a penalty of thousands of gates as it is an entire extra row
in the FU Regs Dependency Matrix.


> > 
> > Have a look at MaskCancellable.
> > 
> > The predicate mask (which is register based) and the stop mask (which is
> > global per pipe) are opaque to the (combinatorial) Stage API.
> 
> that's just fine. think of the multiplier as identical to a combinatorial
> stage except it takes more than one clock cycle for the data to get through.

Not going to fly.

Even without the PartitionSignal concept.

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