[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=123

--- Comment #11 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #10)
> yeh i looked it up, fortunately found a stackexchange resource that
> used double-brackets like this, so i did this:
> 
>             # XXX check! {doSubMags ? ~sigC : sigC,
>             #            {(sigSumWidth - sigWidth + 2){doSubMags}}};
>             sc = [doSubMags] * (sigSumWidth - sigWidth + 2) + \
>                                 [Mux(doSubMags, ~sigC, sigC)]
>             extComplSigC.eq(Cat(*sc))
> 

nmigen has a Repl operator that makes the result much cleaner. It translates
directly to Verilog's repeat construct.

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