[libre-riscv-dev] [Bug 123] IEEE754 FPU FMAC needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=123

--- Comment #10 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #9)
> (In reply to Luke Kenneth Casson Leighton from comment #8)
> >             # XXX check! {doSubMags ? ~sigC : sigC,
> >             #            {(sigSumWidth - sigWidth + 2){doSubMags}}};
> >             extComplSigC.eq(Cat((sigSumWidth - sigWidth + 2){doSubMags}},
> >                                 Mux(doSubMags, ~sigC, sigC))),
> > 
> > anyone know what this translates to?
> 
> I think that's a repeat

yeh i looked it up, fortunately found a stackexchange resource that
used double-brackets like this, so i did this:

            # XXX check! {doSubMags ? ~sigC : sigC,
            #            {(sigSumWidth - sigWidth + 2){doSubMags}}};
            sc = [doSubMags] * (sigSumWidth - sigWidth + 2) + \
                                [Mux(doSubMags, ~sigC, sigC)]
            extComplSigC.eq(Cat(*sc))

so it's 1 bit worth of doSubMags, times ssw-sw+2, with sigC tacked onto the end
(MSB), inverted if doSubMags is true.

possible values:

0b0111111
0b1111111
0b1000000
0b0000000

something like that

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