[libre-riscv-dev] [Bug 76] IEEE754 RISC-V "tininess" as well as rounding modes (odd/even) needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=76

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
http://www.jhauser.us/arithmetic/HardFloat-1/doc/HardFloat-Verilog.html
http://www.jhauser.us/arithmetic/HardFloat.html

source is a .zip archive.  there is an extremely clean and clear function,
roundRawFNtoRecFN in there which has all of the logic for rounding.

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