[libre-riscv-dev] [isa-dev] Re: FP transcendentals (trigonometry, root/exp/log) proposal
luke.leighton at gmail.com
Fri Aug 9 04:26:12 BST 2019
On Thursday, August 8, 2019 at 10:55:27 PM UTC+8, Allen Baum wrote:
> From my point of view, it needs to match the reference model for any ratified standard., else it won’t be labeled compliant.
You mean RV compliance? It also needs to realistically meet customer demand.
In the market dominated by AMD and NVidia that gives one driving factor: compliance with Khronos specifications. Failure to meet these predefined requirements will automatically result in market rejection.
In the embedded GPU market, typically defined as around 1024x768 resolution, sometimes even 14 bit accuracy is completely pointless and just prices the product out of an extremely competitive and lucrative market.
MIPS 3D ASE had a special 12 bit accuracy FPDIV operation that could be called twice in succession. For pixel positions up to around +/-2048 12 bit accuracy works perfectly well.
So the proposal basically has to be flexible enough to recognise Industry Standard market driven requirements.
I received this comment from an offline discussion:
Yes, embedded systems typically can do with 12, 16 or 32 bit accuracy. Rarely does it require 64 bits. But the idea of making a low power 32 bit FPU/DSP that can accommodate 64 bits is already being done in other designs such as PIC etc I believe. For embedded graphics 16 bit is more than adequate. In fact, Cornell had a very innovative 18-bit floating point format described here (useful for FPGA designs with 18-bit DSPs):
A very interesting GPU using the 18-bit FPU is also described here:
More information about the libre-riscv-dev