[libre-riscv-dev] ALU ported over from Verilog to nMigen

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Mon, Aug 5, 2019 at 5:36 AM Samuel Falvo II <sam.falvo at gmail.com> wrote:
>
> Thanks for mentioning Mux; that was most helpful!

http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/4e5c7af7d706e9be
coool, that looks a lot better, doesn't it?

> The ALU is now formally verified (by way of the formal tests of the IXU),

nice!

> and the IXU now implements the operand-fetch and execute steps of the
> entire set of OP-IMM instructions.  Next up is register writeback and
> support for receiving the next instruction to execute.

progress...