[libre-riscv-dev] ALU ported over from Verilog to nMigen

[Samuel Falvo II]

Thanks for mentioning Mux; that was most helpful!

The ALU is now formally verified (by way of the formal tests of the IXU),
and the IXU now implements the operand-fetch and execute steps of the
entire set of OP-IMM instructions.  Next up is register writeback and
support for receiving the next instruction to execute.


On Sun, Aug 4, 2019 at 3:36 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Sun, Aug 4, 2019 at 11:16 PM Samuel Falvo II <sam.falvo at gmail.com>
> wrote:
> >
> >
> http://chiselapp.com/user/kc5tja/repository/kestrel-3/artifact/231dc2c2884b58d6
> >
> > The code has no accompanying tests yet (it will take some time to
> translate
> > the Verilog unit tests over to nMigen).  But, might be worthy of a gander
> > to those interested.
>
>  niice - definitely.
>
> > nMigen's code is significantly more verbose than Verilog in this case,
> even
> > without considering the new set of comments to explain how the stuff
> works.
>
>          lsh4 = Signal(xlen)
>         with m.Switch(self.b[2]):
>             with m.Case(Const(0)):
>                 comb += lsh4.eq(lsh2)
>             with m.Case(Const(1)):
>                 comb += lsh4.eq(Cat(Const(0, 4), lsh2[0:xlen-4]))
>
> could be:
>
>                 comb += Mux(self.b[2], lsh2, lsh4.eq(Cat(Const(0, 4),
> lsh2[0:xlen-4])))
>
> and there's nothing to stop you doing this:
>
>     bin - self.b
>
> or:
>
>      bi = self.b
>
> then reducing the line-length further:
>
>                 comb += Mux(bi[2], lsh2, lsh4.eq(Cat(Const(0, 4),
> lsh2[0:xlen-4])))
>
> also, likewise, you can declare some magic constants z1, z2, z4, z8, z16,
> z32:
>
> z1 = Const(0, 1) # zero of length 1
> z2 = Const(0, 2) # zero of length 2
> z4 = Const(0, 4) # zero of length 4
>
> and get it down *even more*:
>
>             comb += Mux(bi[2], lsh2, lsh4.eq(Cat(z4, lsh2[0:xlen-4])))
>
> and use those tricks everywhere, at which point you'll probably find
> it starts to compact down to the same sort of size as the original
> verilog.
>
> before you do that: if you load the .il file into yosys then do this:
>
> $yosys
> > read_ilang alu.il
> > proc
> > opt
> > show top
>
> you'll find it extremely likely that the switch statements on
> self.b[N] are in fact converted *to* Mux blocks.
>
> l.
>
> _______________________________________________
> libre-riscv-dev mailing list
> libre-riscv-dev at lists.libre-riscv.org
> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
>


-- 
Samuel A. Falvo II