[libre-riscv-dev] [Bug 63] New: queue (FIFO) library routine needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=63

            Bug ID: 63
           Summary: queue (FIFO) library routine needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

queue needed with the following features:

* between 1 and N entries
* first-word write-through capability
* "pipeline" mode which guarantees data delivery once available

note: SyncFIFO in nmigen uses Memory which cannot accept only 1 entry

note: fwft mode *FAILS* on FPGAs, making it necessary to have SyncFIFOBuffered
      on FPGAs, and SyncFIFO on ASICs.  this makes it impossible to go from
      a tested FPGA design straight to an ASIC layout.

current code (adapted to conform to nmigen FIFOInterface API) here:

https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/queue.py;h=e52ab5e9eb74cbd516b5b0daa8681023714055b3;hb=25a0ec563bd7837b43a1d04036b2a5945c97023b

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