[libre-riscv-dev] [Bug 62] New: nmigen-based general-purpose util / data handling / io-control library needed

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=62

            Bug ID: 62
           Summary: nmigen-based general-purpose util / data handling /
                    io-control library needed
           Product: Libre Shakti M-Class
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Source Code
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-riscv-dev at lists.libre-riscv.org
   NLnet milestone: ---

similar to chisel3 util and not quite as generally along the lines
of litex, and augmenting nmigen.lib, a data handling, i/o control,
pipeline-building-block, queues (FIFOs) and general utils library
is needed.

two key pieces of information to decide:

* name of the repo
* name (hierarchy) in python

Subtasks (edit this comment to add, and create sub-bug):

* queue (FIFO) with write-through and support for 1-address entries
* data handling and routing, i/o control and synchronisation
* general small utility routines


links:

* https://github.com/m-labs/nmigen/tree/master/nmigen/lib
* https://chisel.eecs.berkeley.edu/api/3.0.1/chisel3/util/Queue.html
* https://github.com/freechipsproject/chisel3/tree/src/main/scala/chisel3/util
* https://github.com/enjoy-digital/litex/blob/master/litex/gen/common.py

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