[libre-riscv-dev] pinmux in nmigen

[Rishabh Jain]

Hendrik, I think you are pointing to CISC vs RISC debate. I guess, one case
is RISC has simpler instructions which makes hw implementation of  decoding
easier .. but for a complex x86 instruction: it will break to multiple
simple RISC instructions. So, that means processor pipeline executing one
complex instruction or 3-4 simple instructions to do the same task. Here, I
can't intuitively say which one is better in terms of energy! Please
correct me if I am missing something.

I believe Luke was pointing to carryout  the timeline for subtasks which
needs to be completed in 4-5 months.

On Fri 12 Apr, 2019, 7:33 PM Hendrik Boom, <hendrik at topoi.pooq.com> wrote:

> On Fri, Apr 12, 2019 at 01:59:28PM +0100, Luke Kenneth Casson Leighton
> wrote:
> > On Fri, Apr 12, 2019 at 1:51 PM Rishabh Jain <rishucoding at gmail.com>
> wrote:
> > >
> > > one quick question: I checked this link:
> > > https://www.crowdsupply.com/libre-risc-v/m-class while I was reading
> your
> > > post on riscv hw-dev group. It says " With RISC-V being 40% more power
> > > efficient than x86 or ARM...", an eye-opener
> > > for me.
> >
> >  it's down to the use of compressed instructions, resulting in a
> > reduction in cache size.
>
> That makes sense.  But I thought RISC effificiency was originally
> attributed to simpler instruction decoding and simpler mapping of
> instructions to sets of actions.
>
> >
> > > can we put implementation of pinmux in nmigen as a big task for NLnet
> > > foundation proposal?
> >
> >  yes, definitely.  with small subtasks as well.
> >
> > > we can discuss over breaking into milestons .. and have a rough
> timeline
> > > for completion?
> >
> >  the last time it took... what... four to five months?
>
> Four to five months to make the timeline?  Or to carry it out?
>
> -- hendrik
>
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