[libre-riscv-dev] pinmux in nmigen

[Rishabh Jain]

Yes, reduction in cache size means lookup and comparison of tags will
consume less energy. Are u aware of any research showing comparison of
different ISA's with RISCV for energy efficiency? I am curious to
understand how designers do the benchmarking here.

I worked for around 2 months. If I remember correctly, the project started
early and continued till September.


On Fri 12 Apr, 2019, 6:30 PM Luke Kenneth Casson Leighton, <lkcl at lkcl.net>
wrote:

> On Fri, Apr 12, 2019 at 1:51 PM Rishabh Jain <rishucoding at gmail.com>
> wrote:
> >
> > one quick question: I checked this link:
> > https://www.crowdsupply.com/libre-risc-v/m-class while I was reading
> your
> > post on riscv hw-dev group. It says " With RISC-V being 40% more power
> > efficient than x86 or ARM...", an eye-opener
> > for me.
>
>  it's down to the use of compressed instructions, resulting in a
> reduction in cache size.
>
> > can we put implementation of pinmux in nmigen as a big task for NLnet
> > foundation proposal?
>
>  yes, definitely.  with small subtasks as well.
>
> > we can discuss over breaking into milestons .. and have a rough timeline
> > for completion?
>
>  the last time it took... what... four to five months?
>
> l.
>
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