[libre-riscv-dev] barrel processor as I/O and DMA controller

[Jacob Lifshay]

I'd expect it to be able to get to 1GHz or so.

On Wed, Apr 10, 2019, 04:38 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> jacob, hi,
>
> do you think the 5-stage design you're working on could hit the same
> 800mhz target clock rate in 40 to 28nm?  the reason i ask is, it would
> theoretically do double-duty as a DMA controller.
>
> l.
>
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