[libre-riscv-dev] IEEE754 FPU turning into ALU with Reservation Stations

[Aleksandar Kostovic]

Fixed it. Also have let it run for more than 2000 test vectors so it should
be ok :)

On Fri, Apr 5, 2019 at 7:08 AM Aleksandar Kostovic <
alexandar.kostovic at gmail.com> wrote:

> right away
>
> On Fri, Apr 5, 2019 at 7:07 AM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
>> On Fri, Apr 5, 2019 at 6:04 AM Aleksandar Kostovic
>> <alexandar.kostovic at gmail.com> wrote:
>>
>> > fixed the indentation issues.
>>
>> cool, saw that.  so, next, you'll need to run the unit test and sort this:
>>
>> python3 test_mul.py
>> Traceback (most recent call last):
>>   File "test_mul.py", line 38, in <module>
>>     run_simulation(dut, testbench(dut), vcd_name="test_mul.vcd")
>>   File "/home/lkcl/src/riscv/nmigen/nmigen/compat/sim/__init__.py",
>> line 15, in run_simulation
>>     fragment = fragment_or_module.get_fragment()
>>   File "/home/lkcl/src/libreriscv/ieee754fpu/src/add/fmul.py", line
>> 44, in get_fragment
>>     m.d.comb += a.v.eq(self.a.v)
>> AttributeError: 'FPMUL' object has no attribute 'a'
>>
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>