[libre-riscv-dev] Fwd: spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

ok so this:

loop:
 setvl a0, 4 # vl= min(min(mvl, 4, a0))
 ld    a3, a1    # load 4 registers a3-6 from x
 slli  t1, t0, 3 # t1 = vl * 8 (in bytes)
 ld    a7, a2    # load 4 registers a7-10 from y


would be changed to this:

 setmvl #4 # actually CSRRWI x0, CSR_SV_MVL, #4
loop:
 setvl a0, 4 # vl= min(min(mvl, 4, a0))
 ld    a3, a1    # load 4 registers a3-6 from x
 slli  t1, t0, 3 # t1 = vl * 8 (in bytes)
 ld    a7, a2    # load 4 registers a7-10 from y

which is slightly annoying however at least there's no need for a
special opcode "setvl".  what i plan also to do is to add a
"CSR_SV_REALVL" which will allow save/restore context swapping with a
single instruction.

the next phase is to allow set/get of the register and predication CSR
tables, and i will be able to start writing unit tests.

l.