[libre-riscv-dev] Fwd: spike simple-v implementation, refinement needed

[Luke Kenneth Casson Leighton]

On Sat, Sep 29, 2018 at 12:40 AM, Jacob Lifshay
<programmerjake at gmail.com> wrote:

> I may have missed something, but since sv uses virtual simd when it needs
> to, what's the point of having mvl at all? VL should take care of
> everything.

 it's quite a logical progression / fit - bear with me.

 * CSR writing has to conform to a very specific pattern:  CSRRW rd, CSRnum, rs

 * so, the old version of RVV used CSRRW as a pseudoop:
   SETVL t0, a5  # t0= VL = MIN(MVL, a5)
   was actually encoded as:
   CSRRW t0, CSRRVVSETVL, a5

* however (A) that turns out to be a change to the behaviour of CSR setting,
  which says you need to return the OLD value, NOT the NEW value.

* however (B) SV needs an *extra* argument, the MVL, because MVL is
  *not* hard-coded, it's a runtime parameter.  so i initially did this:
  SETVL t0, a5, 4 # 4==number of registers to use

* however that does *NOT* fit into the CSRRW pattern.

initially i thought about using 32 CSRs and using CSRRWI instead,
however given that there's still a table needed for setting the
per-register *and* per-predicate vector config there's actually the
danger of running out of CSRs as there's only 256 of them available.

i really *really* do not want to have to add an actual instruction, so
there are two compromises to make:

(1) to alter the behaviour of CSRRW so that it does in fact return the new value

(2) to add a new CSR "CSR_SVSETMVL" which unfortunately means one
extra instruction on setting up loops, however it could hypothetically
just be left at e.g. "4" permanently (globally).

 basically it's down to the fact that SV can set arbitrary-length
vector runs, spanning an arbitrary user-selected size of contiguous
registers (up to XLEN bitlength), where RVV is very very specifically
hard-coded to the *LANE* length and the user gets no choice in the
matter.  with no choice in the matter, RVV can have MVL as a
hard-coded parameter.

l.