[libre-riscv-dev] elwidth override on LOAD/STORE

[Luke Kenneth Casson Leighton]

On Sat, Oct 27, 2018 at 11:13 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> however, there are *two* registers involved: RS1 and RD (or FRD in the
> case of FLD/FSD).  and *both* of those can have different elwidths,
> both could (independently) have isvector set, both could have
> packed-SIMD set/unset.
>
> i might actually need to write this out as a huge table, listing what
> to do in each case.  yuk.

ok so i wrote up a sub-section on LOAD/STORE bitwidth polymorphism,
https://libre-riscv.org/simple_v_extension/specification/#elwidth_loadstore

it turned out not to be necessary to write out a huge table, and also
that the difference between the operation's bitwidth and the element
bitwidth is a vital strategic piece of information.

divide one by the other and that determines the number of elements in
each LOAD/STORE memory operation.  however, where it could get complex
is where that division (as an integer) equals zero, in other words the
LOAD operation's width is *LESS* than the element's width.

it turns out that what's needed when this occurs is exactly what LB
and LBU are designed to do by default, anyway: sign/zero-extend the 8
(or 16 or 32) bit data out to the full width of the target register...

... except that the target will *not* necessarily be a *register* but
a *part* of a register.

so i believe the full complete pseudo-code (except for zeroing on
predication) is there, review and comments appreciated.

l.