[libre-riscv-dev] elwidth override on LOAD/STORE

[Luke Kenneth Casson Leighton]

i'm thinking about how element width affects LOAD/STORE, and i believe
the rules should be as follows, taking into account the "packed SIMD",
"isvector" and "element width".  now, if it was single-predicated
(single operand), no problem, it would be like this:

* if elwidth == default, LD/ST is as-is.  8-bit LD equals 8-bit LD.
operand gets zero-extended for LBU, and sign-extended for LB etc.
* if "packed SIMD", it's a *batch* of LD/STs. the batch size is the
width of the LD operation divided by elwidth.
* if isvector == false, the destination will be zero-extended /
sign-extended to the target elwidth.

however, there are *two* registers involved: RS1 and RD (or FRD in the
case of FLD/FSD).  and *both* of those can have different elwidths,
both could (independently) have isvector set, both could have
packed-SIMD set/unset.

i might actually need to write this out as a huge table, listing what
to do in each case.  yuk.

:)

before doing that, does anyone have any thoughts / insights?

l.