[libre-riscv-dev] RVV setting VL to zero, what happens?

[Luke Kenneth Casson Leighton]

(please disregard, meant to send to isa-dev)
On Wed, Oct 17, 2018 at 2:42 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
>
> in the example pseudo-code listed here
>   https://www.sigarch.org/simd-instructions-considered-harmful/
>
> there's a potential missing corner-case at the start, and it's where n
> is zero.   has this been taken into account in the design of RVV?
>
> l.