[libre-riscv-dev] New Person

[lkcl]

On Sun, Oct 14, 2018 at 12:30 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
>
> It turns out the sv branch I had created branched from master and not
> origin/sv! Shame on me.
>
> Rather than running
>
> > git checkout -b sv
> >

 aw doh! :)  yeah apologies, i didn't anticipate that :)

> I ran
>
> > git branch sv origin/sv
> >
> followed by
>
> > git checkout sv
> >
> to properly link my local branch to the remote sv branch.
>
> This had to be done for BOTH of the cloned repositories as both were wrong.

 yes, expected

> As a side note, in the incorrectly branched version whenever I ran 'make
> install' it overrides the spike related data found in: $RISCV/bin,
> $RISCV/lib, and, $RISCV/include. I would not get anything populated in:
> usr/local/bin, usr/local/lib, or, usr/local/include.

 that's interesting.

> Though this is a
> problem that doesn't exist anymore as nothing works so... one less issue
> right! :)
>
> When I attempt to 'make' the sv branch of riscv-isa-sim from the /build
> folder (after branching correctly) I recieve the following error:
>
> The initial error generated by the first make was:
>
> > ../riscv/gen_icache `grep "ICACHE_ENTRIES =" ../riscv/mmu.h | sed 's/.* =
> > \(.*\);/\1/'` > icache.h.tmp
> > mv icache.h.tmp icache.h
> > for insn in add addi addiw addw amoadd_d amoadd_w amoand_d amoand_w
> > amomax_d amomaxu_d amomaxu_w amomax_w amomin_d amominu_d amominu_w amomin_w
> > amoor_d amoor_w amoswap_d amoswap_w amoxor_d amoxor_w and andi auipc beq
> > bge bgeu blt bltu bne c_add c_addi4spn c_addi c_addw c_and c_andi c_beqz
> > c_bnez c_ebreak c_fld c_fldsp c_flw c_flwsp c_fsd c_fsdsp c_fsw c_fswsp
> > c_jal c_jalr c_j c_jr c_li c_lui c_lw c_lwsp c_mv c_or c_slli c_srai c_srli
> > c_sub c_subw c_xor csrrc csrrci csrrs csrrsi csrrw csrrwi c_sw c_swsp div
> > divu divuw divw dret ebreak ecall fadd_d fadd_q fadd_s fclass_d fclass_q
> > fclass_s fcvt_d_l fcvt_d_lu fcvt_d_q fcvt_d_s fcvt_d_w fcvt_d_wu fcvt_l_d
> > fcvt_l_q fcvt_l_s fcvt_lu_d fcvt_lu_q fcvt_lu_s fcvt_q_d fcvt_q_l fcvt_q_lu
> > fcvt_q_s fcvt_q_w fcvt_q_wu fcvt_s_d fcvt_s_l fcvt_s_lu fcvt_s_q fcvt_s_w
> > fcvt_s_wu fcvt_w_d fcvt_w_q fcvt_w_s fcvt_wu_d fcvt_wu_q fcvt_wu_s fdiv_d
> > fdiv_q fdiv_s fence fence_i feq_d feq_q feq_s fld fle_d fle_q fle_s flq
> > flt_d flt_q flt_s flw fmadd_d fmadd_q fmadd_s fmax_d fmax_q fmax_s fmin_d
> > fmin_q fmin_s fmsub_d fmsub_q fmsub_s fmul_d fmul_q fmul_s fmv_d_x fmv_w_x
> > fmv_x_d fmv_x_w fnmadd_d fnmadd_q fnmadd_s fnmsub_d fnmsub_q fnmsub_s fsd
> > fsgnj_d fsgnj_q fsgnjn_d fsgnjn_q fsgnjn_s fsgnj_s fsgnjx_d fsgnjx_q
> > fsgnjx_s fsq fsqrt_d fsqrt_q fsqrt_s fsub_d fsub_q fsub_s fsw jal jalr lb
> > lbu ld lh lhu lr_d lr_w lui lw lwu mret mul mulh mulhsu mulhu mulw or ori
> > rem remu remuw remw sb sc_d sc_w sd sfence_vma sh sll slli slliw sllw slt
> > slti sltiu sltu sra srai sraiw sraw sret srl srli srliw srlw sub subw sw
> > wfi xor xori ; do \
> >     printf 'DEFINE_INSN(%s)\n' "${insn}" ; \
> > done > insn_list.h.tmp
> > mv insn_list.h.tmp insn_list.h
> > python sv_proc_gen.py
> > python: can't open file 'sv_proc_gen.py': [Errno 2] No such file or
> > directory
> > riscv.mk:309: recipe for target 'insn_list.h' failed
> > make: *** [insn_list.h] Error 2
> >

 https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=blob;f=sv_proc_gen.py;h=13eddaf3f926f26803c07eaaf304d7846b1d69d6;hb=refs/heads/sv

 it's definitely there.  try a "git pull" now that you're on the right
branch.  also check with "git log" that you're completely up-to-date:
 https://git.libre-riscv.org/?p=riscv-isa-sim.git;a=shortlog;h=refs/heads/sv


> All subsequent attempts to call 'make' resulted in the following output:

 yep... no point continuing if sv_proc_gen.py can't generate the
header file that's needed.

> Would you know by any chance where I might steal/find this mystical include?

 it's made by sv_proc_gen.py, so if that file's not present, you don't
get that header file.  simple.

> The same can be said for the riscv-tests I had the wrong branch again!
> Though calling make works for the sv version of risv-tests just fine, when
> calling 'make run' it fails and outputs the following:

 yep.  main version of spike is completely incapable of running
simple-v unit tests.  it is absolutely guaranteed to fail, so you have
repro'd the "correct" outcome, here.

> > spike --isa=rv64gc rv64ui-p-sv_addi 2> rv64ui-p-sv_addi.out
> > Makefile:52: recipe for target 'rv64ui-p-sv_addi.out' failed
> > make: *** [rv64ui-p-sv_addi.out] Error 156
> >
>
>
> Some progress as to why no output was appearing at least! All tools within
> riscv-tools function properly. The tests for riscv-tools also pass without
> any alarms.
>
> Hopefully this is not another issue on my end and I branched correctly this
> time!

 i'm guessing you forgot to do a "git pull" after doing the branch.

 have a look in the .git/config file, it should look something like this:

[remote "origin"]
    #url = https://github.com/riscv/riscv-isa-sim.git
    url = gitolite3 at libre-riscv.org:riscv-isa-sim
    fetch = +refs/heads/*:refs/remotes/origin/*
[branch "master"]
    remote = origin
    merge = refs/heads/master
    rebase = true
[branch "sv"]
    remote = origin
    merge = refs/heads/sv
    rebase = true

and if it does, then when you do "git pull", as long as you have the
sv branch checked out you should get the right stuff.

l.