[libre-riscv-dev] New Person

[Daniel Benusovich]

It turns out the sv branch I had created branched from master and not
origin/sv! Shame on me.

Rather than running

> git checkout -b sv
>

I ran

> git branch sv origin/sv
>
followed by

> git checkout sv
>
to properly link my local branch to the remote sv branch.

This had to be done for BOTH of the cloned repositories as both were wrong.

As a side note, in the incorrectly branched version whenever I ran 'make
install' it overrides the spike related data found in: $RISCV/bin,
$RISCV/lib, and, $RISCV/include. I would not get anything populated in:
usr/local/bin, usr/local/lib, or, usr/local/include. Though this is a
problem that doesn't exist anymore as nothing works so... one less issue
right! :)

When I attempt to 'make' the sv branch of riscv-isa-sim from the /build
folder (after branching correctly) I recieve the following error:

The initial error generated by the first make was:

> ../riscv/gen_icache `grep "ICACHE_ENTRIES =" ../riscv/mmu.h | sed 's/.* =
> \(.*\);/\1/'` > icache.h.tmp
> mv icache.h.tmp icache.h
> for insn in add addi addiw addw amoadd_d amoadd_w amoand_d amoand_w
> amomax_d amomaxu_d amomaxu_w amomax_w amomin_d amominu_d amominu_w amomin_w
> amoor_d amoor_w amoswap_d amoswap_w amoxor_d amoxor_w and andi auipc beq
> bge bgeu blt bltu bne c_add c_addi4spn c_addi c_addw c_and c_andi c_beqz
> c_bnez c_ebreak c_fld c_fldsp c_flw c_flwsp c_fsd c_fsdsp c_fsw c_fswsp
> c_jal c_jalr c_j c_jr c_li c_lui c_lw c_lwsp c_mv c_or c_slli c_srai c_srli
> c_sub c_subw c_xor csrrc csrrci csrrs csrrsi csrrw csrrwi c_sw c_swsp div
> divu divuw divw dret ebreak ecall fadd_d fadd_q fadd_s fclass_d fclass_q
> fclass_s fcvt_d_l fcvt_d_lu fcvt_d_q fcvt_d_s fcvt_d_w fcvt_d_wu fcvt_l_d
> fcvt_l_q fcvt_l_s fcvt_lu_d fcvt_lu_q fcvt_lu_s fcvt_q_d fcvt_q_l fcvt_q_lu
> fcvt_q_s fcvt_q_w fcvt_q_wu fcvt_s_d fcvt_s_l fcvt_s_lu fcvt_s_q fcvt_s_w
> fcvt_s_wu fcvt_w_d fcvt_w_q fcvt_w_s fcvt_wu_d fcvt_wu_q fcvt_wu_s fdiv_d
> fdiv_q fdiv_s fence fence_i feq_d feq_q feq_s fld fle_d fle_q fle_s flq
> flt_d flt_q flt_s flw fmadd_d fmadd_q fmadd_s fmax_d fmax_q fmax_s fmin_d
> fmin_q fmin_s fmsub_d fmsub_q fmsub_s fmul_d fmul_q fmul_s fmv_d_x fmv_w_x
> fmv_x_d fmv_x_w fnmadd_d fnmadd_q fnmadd_s fnmsub_d fnmsub_q fnmsub_s fsd
> fsgnj_d fsgnj_q fsgnjn_d fsgnjn_q fsgnjn_s fsgnj_s fsgnjx_d fsgnjx_q
> fsgnjx_s fsq fsqrt_d fsqrt_q fsqrt_s fsub_d fsub_q fsub_s fsw jal jalr lb
> lbu ld lh lhu lr_d lr_w lui lw lwu mret mul mulh mulhsu mulhu mulw or ori
> rem remu remuw remw sb sc_d sc_w sd sfence_vma sh sll slli slliw sllw slt
> slti sltiu sltu sra srai sraiw sraw sret srl srli srliw srlw sub subw sw
> wfi xor xori ; do \
>     printf 'DEFINE_INSN(%s)\n' "${insn}" ; \
> done > insn_list.h.tmp
> mv insn_list.h.tmp insn_list.h
> python sv_proc_gen.py
> python: can't open file 'sv_proc_gen.py': [Errno 2] No such file or
> directory
> riscv.mk:309: recipe for target 'insn_list.h' failed
> make: *** [insn_list.h] Error 2
>

All subsequent attempts to call 'make' resulted in the following output:

> g++ -fPIC -MMD -MP -I/home/daniel/Documents/riscv-toolchain/include  -Wall
> -Wno-unused -g -O2 -std=c++11
> -DPREFIX=\"/home/daniel/Documents/riscv-toolchain\" -I. -I.. -I../riscv
> -I../dummy_rocc -I../softfloat -I../operators -I../spike_main -x c++-header
> ../riscv/insn_template.h -o insn_template.h.gch
> In file included from ../riscv/processor.h:15:0,
>                  from ../riscv/mmu.h:11,
>                  from ../riscv/insn_template.h:3:
> ../riscv/sv_insn_redirect.h:62:10: fatal error: sv_insn_decl.h: No such
> file or directory
>  #include "sv_insn_decl.h"
>           ^~~~~~~~~~~~~~~~
> compilation terminated.
> Makefile:319: recipe for target 'insn_template.h.gch' failed
> make: *** [insn_template.h.gch] Error 1
>

Would you know by any chance where I might steal/find this mystical include?

The same can be said for the riscv-tests I had the wrong branch again!
Though calling make works for the sv version of risv-tests just fine, when
calling 'make run' it fails and outputs the following:

> spike --isa=rv64gc rv64ui-p-sv_addi 2> rv64ui-p-sv_addi.out
> Makefile:52: recipe for target 'rv64ui-p-sv_addi.out' failed
> make: *** [rv64ui-p-sv_addi.out] Error 156
>


Some progress as to why no output was appearing at least! All tools within
riscv-tools function properly. The tests for riscv-tools also pass without
any alarms.

Hopefully this is not another issue on my end and I branched correctly this
time!
Let me know what are the next steps to take to fix the issue.

On Thu, Oct 11, 2018 at 11:07 PM Daniel Benusovich <
flyingmonkeys1996 at gmail.com> wrote:

> I edited the spike.cc found in the spike-sv riscv-isa-sim version and
> added ye old verification (a printf) to see if I was running the correct
> spike version and viola output! I was able to run the commands directly via
> spike after running "make clean" on riscv-tools/riscv-isa-sim/build and
> "make install" on riscv-isa-sim/build (the lbre version). Flipping the
> process would not cause the printout to me confirming that something good
> is happening. I did not discover where the debug output you spoke of was
> sent to; if it goes to the console then I am still very much lost! If it
> does not go to the console do let me know where it is stored so I can
> search for it.
>
> If this is all correct do tell me what to fuss over next. I will happily
> add to the installation procedure docs so that my mother could try and
> install this as well if i did it correctly haha.
>
> On Wed, Oct 10, 2018 at 11:49 PM Daniel Benusovich <
> flyingmonkeys1996 at gmail.com> wrote:
>
>> If I clone the risv-isa-sim repo from libre into a seperate directory,
>> seperate from the riscv-tools repo, and run make install within
>> risv-isa-sim from libre will the spike executable default to the
>> risv-isa-sim libre version or the version provided within riscv-tools?
>>
>> Both compiled correctly and this seems to be the last step. However, I am
>> not certain the correct sim is being called as both simulators have been
>> built. I called 'make clean" on the riscv-tools/riscv-isa-sim/build while
>> leaving the risv-isa-sim libre version build folder alone and was able to
>> run a hello world via the spike simulator. Would this be a sign of success?
>>
>>
>> On Tue, Oct 9, 2018 at 10:58 PM Daniel Benusovich <
>> flyingmonkeys1996 at gmail.com> wrote:
>>
>>> I was able to setup the tools (using the master branch), the libre
>>> repositories, and complete the instructions found here:
>>> https://libre-riscv.org/3d_gpu/spike_sv/
>>>
>>> Thankfully no need for any additional tools to set everything up from
>>> riscv-tools for elf-gcc-7.2.0 or elf-gcc, just good old build scripts
>>> provided by the repository.
>>>
>>> I can confirm that both the RISCV and the PATH variables must be set
>>> prior to running the unit tests in riscv-tests. Are the resulting output
>>> files expected to be empty? A flurry of the buggers were generated but they
>>> are empty; though my guess is these tests exist to verify that all the
>>> includes and whatnot were generated properly.
>>>
>>> In addition I was able to compile and run a Hello World program using
>>> the elf-gcc-7.2.0/elf-gcc and spike simulator respectively. I am pretty
>>> sure the simulator is using the stock riscv-isa-sim and not the augmented
>>> version provided by libre. A task for tomorrow indeed.
>>>
>>> It would be good to move the setting of the RISCV and PATH variables to
>>> the top of the installation procedure. Would've saved a bit of a headache.
>>> Also a link to the riscv-tools would've made things a tad bit easier:
>>> https://github.com/riscv/riscv-tools and specification on which branch
>>> should or could be used (master in my case).
>>>
>>> I will try messing around reinstalling everything again tomorrow and
>>> have a more comprehensive guide on how it should work including trying to
>>> use the libre augmented spike simulator rather than the riscv-tools version.
>>>
>>> Hope you are having a good one!
>>>
>>>
>>>
>>> On Mon, Oct 8, 2018 at 10:22 PM Daniel Benusovich <
>>> flyingmonkeys1996 at gmail.com> wrote:
>>>
>>>> Yes that clears up my questions thank you!
>>>>
>>>> I look forward to being the second person in the world (maybe) to make
>>>> something work haha.
>>>>
>>>> I will keep you posted on any progress or roadblocks that appear. Thank
>>>> you for your time and patience!
>>>>
>>>> - Daniel B.
>>>>
>>>> On Sun, Oct 7, 2018 at 11:39 PM lkcl <lkcl at libre-riscv.org> wrote:
>>>>
>>>>> On Mon, Oct 8, 2018 at 4:43 AM Daniel Benusovich
>>>>> <flyingmonkeys1996 at gmail.com> wrote:
>>>>> >
>>>>> > I have a few questions on the environment.
>>>>> >
>>>>> > riscv-tools repository has a version of Spike. Is the same one
>>>>> contained
>>>>> > in the libre-riscv repository a fork of that one?
>>>>>
>>>>>  yes it is.  so, if compiling the standard riscv-tools succeeds (there
>>>>> are some automated build scripts to do so), it would then just be a
>>>>> matter of "git checkout -b sv"
>>>>>
>>>>> >  I noticed it does have the libre-riscv repository version has a
>>>>> > description stating it is an augmented version but I just want to be
>>>>> sure.
>>>>>
>>>>>  yep, you're right.
>>>>>
>>>>> > What you asked me to document is the process of creating a
>>>>> > development environment that one can use to compile and
>>>>> > then run a sample program using the simulator correct?
>>>>>
>>>>>  the unit tests - riscv-tests/isa with "make run", yes.
>>>>>
>>>>> > The instructions on the page detail vaguely how to set it up but
>>>>> > not how to verify the installation or compile/run any programs
>>>>> > which I am guessing is the missing documentation that needs to be
>>>>> done.
>>>>>
>>>>>  yup :)  or, just the very fact that you're asking the questions means
>>>>> i will put in some notes (like i have now), as that illustrates to me
>>>>> the things that i know which haven't been recorded.
>>>>>
>>>>> > Also are the unit tests that need work regarding the Spike simulator
>>>>> > or another component of the project?
>>>>>
>>>>>  ok so the riscv-tests unit tests are generic, they can be used
>>>>> anywhere, for any purpose, to test any simulator or any real hardware.
>>>>> it would be possible to run them on an FPGA, under verilator:
>>>>> anything.
>>>>>
>>>>>  so, therefore, i *happen* to be using them to bootstrap spike-sv up
>>>>> to a working implementation, making sure that as i add new
>>>>> functionality i don't break the old stuff.
>>>>>
>>>>>  once that's up and running, and spike-sv is stable, i can look at
>>>>> other areas, and perhaps we could ask jacob if he needs help
>>>>> documenting what he's doing.
>>>>>
>>>>>  once you have a working dev-environment and "make run" on the isa
>>>>> tests passes (which will be worth celebrating on its own, you'd be i
>>>>> think only the second person in the world to do so), we can discuss
>>>>> further what you'd like to do.
>>>>>
>>>>> > If it is the Spike sim unit tests need work is it the tests in the
>>>>> riscv-tools repository or the libre-riscv repository?
>>>>>
>>>>>  the two libre-riscv repositories riscv-isa-sim and riscv-tests are
>>>>> forks of two of the riscv-tools repositories.  adding sv unit tests to
>>>>> the standard riscv-tools repository would not be useful to do, as the
>>>>> standard riscv-tools repository knows absolutely nothing about sv.
>>>>> hence why i have forked them.
>>>>>
>>>>> hope that clarifies?
>>>>>
>>>>> l.
>>>>>
>>>>