[libre-riscv-dev] HDL selection

[lkcl]

Cat(Replicate(fetch_pc[2], 20), fetch_pc[2:])

produces this:

   {fetch_pc[31:2], {20{fetch_pc[2]}}}

which will be important for cpu_decoder.v in calculating the immediate value:

  {{20{instruction[31]}}, instruction[31:20]}

would be something like:

Cat(fetch_pc[20:], Replicate(instruction[31], 20))

we have to watch out for that: migen uses python slice syntax
(LSB:MSB+1) where verilog uses [MSB:LSB] inclusive on both.  and, Cat
is inverted as well, it starts from LSB where verilog starts from MSB.

l.