[libre-riscv-dev] HDL selection

[lkcl]

On Thu, Nov 22, 2018 at 12:33 AM lkcl <lkcl at libre-riscv.org> wrote:
>
> https://git.libre-riscv.org/?p=rv32.git;a=blob;f=cpu_fetch_stage.py
>
> urk.  slightly struggling, getting there.  asked florian
> (enjoy-digital) for a bit of advice, and he says that @posedge clk and
> reset are equivalent to adding to "sync" (amongst other really useful
> things).

i spoke to florian again, he confirmed that @always posedge clk or
posedge reset is "self.sync +=", and that anything within such blocks
that test "if reset" are the "reset" argument to Signal.  so this:

     always @(posedge clk or posedge reset) begin
        if(reset)
            delayed_instruction_valid <= 0;
        else
            delayed_instruction_valid <= fetch_action == `fetch_action_wait;
    end

becomes this:

        delayed_instruction_valid = Signal(reset=0)
        self.sync += delayed_instruction_valid.eq(fetch_action ==
                                                  fetch_action_wait)

this file is nearly at the point where it might be a valid python
program, so i will be able to run it and see what the verilog output
looks like, soon.

jacob, daniel, would you like to have a go at converting one of the cpu files?

l.