[libre-riscv-dev] HDL selection

[lkcl]

https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py

this is fascinating (it's pyRTL, not migen) - an OO way to create a
pipeline, where the overload of setattr and getattr automatically
creates *different* underlying signals (registers in pyrtl's case)
than what was "asked" for.  if that makes any sense.

one of the cool things about python is that if a class has an
__setattr__ method, if you do "self.x = 5" then instead of creating a
variable "x" as a member of the class, the class's __setattr__ method
is called instead, with the string "x" as the name and the integer
value 5 in this example.

that basically allows you to do anything... including, by locating the
methods (line 19), walking through them (line 20), and calling them
(line 22), you can prepare the *next* phase (line 58) with some hidden
registers that encode the name of the stage in them (lines 39 and 40),
and store a reference to the (hidden) register (line 44).

so, within each stage function (as called from __init__, at line 22),
the use of any variable will result in the use of the register within
that stage, but *assignment* will create a *NEW* register for use in
the *NEXT* stage.  then the stage num is incremented (line 23), and
the next stage is called (line 22)... and it gets to use the registers
assigned from the *PREVIOUS* stage.

oh... and yet all the variable names remain the same at the python
code level, saving the developer from having to have explicit naming
of registers propagate up to the code level.

the alternative:

def stage0():
    self.n_register_0_to_next_stage_1 = Signal()
    self.n_register_0_to_next_stage_1.eq(n_register_0)

def stage1():
    self.n_register_1_to_next_stage_2 = Signal()
    blah blah

all of that crud disappears.

utterly, utterly cool.

l.