[libre-riscv-dev] HDL selection

[lkcl]

https://git.libre-riscv.org/?p=rv32.git;a=blob;f=cpu_fetch_stage.py

urk.  slightly struggling, getting there.  asked florian
(enjoy-digital) for a bit of advice, and he says that @posedge clk and
reset are equivalent to adding to "sync" (amongst other really useful
things).

if i can get to the point where the above compiles, i can start doing
a comparison of the auto-generated verilog against the original.

i should have picked a smaller file to start with (cpu_alu.v for example).

i checked in the implementation of Case:
https://github.com/m-labs/migen/blob/master/migen/fhdl/structure.py#L591

yes you can pass a list of statements.

also there is clocks and ClockDomains, which will be *really* useful
(essential).


he also pointed me towards some socs, which, if we use the misoc
library, should save a *lot* of time:
https://github.com/m-labs/misoc/blob/master/misoc/cores/gpio.py

CSRStatus, CSRStorage, MultiReg classes, those look really handy.

also there's a pll class in there as well, somewhere.

l.