[libre-riscv-dev] HDL selection

[Jacob Lifshay]

On Tue, Nov 20, 2018 at 8:02 PM lkcl <lkcl at libre-riscv.org> wrote:

> On Wed, Nov 21, 2018 at 1:16 AM lkcl <lkcl at libre-riscv.org> wrote:
> >
> > On Wed, Nov 21, 2018 at 12:35 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
>
> > > From what I can tell, Chisel is actually very similar in design to
> Migen in
> > > that both of them are programs that use a HDL library to build an AST
> for
> > > the HDL at runtime and the only major difference is that Migen is
> written
> > > in Python and Chisel is written in Scala.
> >
> >  interesting.
>
>  https://m-labs.hk/migen/manual/fhdl.html
>
>  looks like, whilst myhdl uses the python AST (hence the close tie-in
> to python syntax), migen has a series of objects "If", "Case",
> "Signal" and so on that are chained together to form an object tree.
>
> at the top level of that object tree you get to call a function
> "convert" which returns an object that contains a function "write".
> that function happens to output verilog (or vhdl).
>
>  myhdl, you actually have actual python code instead of an object
> tree, where the python code has to be converted to python AST, and the
> python AST is passed to a language translator that happens to output
> verilog.
>
That's one of the reasons that I didn't want to use MyHDL since python is
not designed to be a HDL, I would say that MyHDL is abusing Python's
syntax, making it a confusing combination of an HDL and Python. Migen, by
contrast, keeps the HDL portion separate from Python's syntax, allowing
more design freedom.

Jacob