[Libre-soc-isa] [Bug 1161] EXTRA2/3 algorithm likely inconsistent with EXTRA2 tables causing PowerDecoder2 and insndb to disagree on scalar EXTRA2 register encoding for >=r32

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1161

--- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #0)
> I discovered this by running:
> sv.maddedu *4, *32, 36, 8
> and was confused by why it kept reading RB from register 68 not 36

now that I think about a bit more, PowerDecoder2 must be incorrect, since r68
shouldn't even be encodeable.

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