[Libre-soc-isa] [Bug 533] New: design new CR instructions suitable for predication

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=533

            Bug ID: 533
           Summary: design new CR instructions suitable for predication
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-November/001335.html

if using CRs, beq/bgt/blt makes decisions based on a single bit analysis (and
inversion) of a CR, which frequently requires a crand/cror op prior to get
branch conditions that otherwise do not exist in single-instruction form.

the idea here is to create a combined CR analysis operation that makes multiple
bits [0-3] of a CR and creates a single bit yes/no, extending what crand/cror
(etc) currently do.

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