[Libre-soc-isa] [Bug 564] New: add SV variant of fcvt to deal with elwidth differences in OpenPOWER FP scalar formats

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=564

            Bug ID: 564
           Summary: add SV variant of fcvt to deal with elwidth
                    differences in OpenPOWER FP scalar formats
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

https://bugs.libre-soc.org/show_bug.cgi?id=560#c32

this one is... annoying/tedious/necessary.

elwidth overrides when srcwid!=destwid are such a performance killer due to
lane crossing that it is better to perform an "in-advance conversion" to make
the bitwidth the same across src and dest than it is to do lane-crossing.

in addition, OpenPOWER Scalar FP32 fits across the bits of a FP64 to make it
look as if it was actually an FP64.

both RVV and VSX perform fcvt conversion such that packed FP32 is easy and
routine.

fcvt capability is therefore required somehow.  the most sensible method is
adding an explicit opcode, although there are other methods.

one interesting option for fcvt is to also combine it with fclass (storing the
analysis bits in CR1) when Rc=1

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