[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

Jacob Lifshay <programmerjake at gmail.com> changed:

           What    |Removed                     |Added
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                 CC|                            |programmerjake at gmail.com

--- Comment #4 from Jacob Lifshay <programmerjake at gmail.com> ---
We should try to make it so storing a vector of one type to memory then loading
those same bytes as a vector of a different type can be optimized to just
reinterpreting the in-register representation, no byte-swap instructions
needed.

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