[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
lxo: my other issue is about mapping vector operations that operate on
sub-register vector elements (say bytes) onto loops over insns, when there are
*not* insns that operate on sub-register parts

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